1. Field of the Invention
The present invention relates generally to complementary insulated gate field effect transistor structures and processes for fabricating them. More particularly, this invention relates to an improved method for fabricating CMOS devices which results in higher density integrated circuits having greater reliability.
2. Description of the Prior Art
Complementary insulated gate field effect transistor (FET) circuit arrangements employ an n-channel FET and a p-channel FET which usually have commonly connected gates, and the source or drain of one transistor connected to the source or drain of the other transistor. Connected as such, the two transistors require signals of opposite polarity for conduction, and in any mode of circuit operation, one of the transistors will be on while the other will be off. Therefore little current will flow from the power supply to ground. When operating conditions within the overall circuit containing the CMOS device require that the "on" transistor be switched off, the transistor which was previously off will be switched on due to interconnection of the gates and either the sources or the drains of the two complementary transistors. This concept was first disclosed by Wanlass in U.S. Pat. No. 3,356,858, assigned to the assignee of the present invention. CMOS devices are particularly useful because no additional power is required to switch the transistors of the complementary pair. Switching is an inherent attribute of CMOS device operation.
Conventional CMOS structures have been fabricated with conducting interconnections between particular sources and drains of the n-channel and p-channel transistors. The conductors may be metal, but more recently have been conductive polycrystalline silicon. Silicon dioxide is the most widely used insulator in CMOS devices and single crystal silicon is the most widely used semiconductor substrate.
CMOS structures are usually fabricated in an N conductivity type silicon substrate rather than in a P-type substrate because it is easier to obtain desirable threshold voltages for both the n-channel and the p-channel complementary devices in an n-type substrate. A region or well of p-type conductivity is formed in the n-type substrate to accommodate the n-channel transistor.
CMOS structures typically utilize a single layer of polycrystalline silicon and a single layer of aluminum as interconnections. Certain other integrated circuit technologies utilize a first polycrystalline silicon layer as gate electrodes and electrical interconnections, a second polycrystalline silicon layer as high resistivity resistors, and a layer of aluminum as interconnections. Prior art CMOS fabrication techniques typically utilize photoresist for masking heavy ion implantations.